Transport Properties of Silicene Nanotube- and Silicene Nanoribbon-Based FETs

Transport Properties of Silicene Nanotube- and Silicene Nanoribbon-Based FETs

Deep Kamal Kaur Randhawa (Guru Nanak Dev University, Regional Campus, Jalandhar, India), Paramjot Singh (Guru Nanak Dev University, Regional Campus, Jalandhar, India) and Tarun (Guru Nanak Dev University, Regional Campus, Jalandhar, India)
DOI: 10.4018/978-1-7998-1393-4.ch010

Abstract

Silicene is one of the most interesting nanomaterials. In this chapter, computational studies have been done on Silicene nanotube and nanoribbon-based FETs to analyze their transport properties. The FET is designed from armchair nanoribbon and single wall nanotube. The scattering region is capped by a dielectric and a metallic layer to form a gate. The conductance versus gate bias voltage, conductance versus temperature up to 2000K, and electrode temperature versus current characteristics are calculated and plotted along with the design of the equivalent model of the structure. Extended Huckel-based calculations were used, and the analysis shows the transport properties of both structures.
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1.1 Introduction

Electrical and electronic devices initially comprised of two terminal devices, in which current flowed from one terminal to the other terminal. With development of technology three terminal devices were devised which we could control the flow of current between two terminals by the third terminal. Under category of three terminals devices, two models are widely accepted that is, Bipolar Function Transistor (BJT) and Field Effect Transistor (FET). FET is more widely used in Integrated circuits (ICs) as compare to BJT virtue its better electronic characteristics. The introduction of Field effect Transistors (FET) in the field of electronics has revolutionized the industry as the second revolution in electronics was introduced by the introduction of MOSFET’s in high speed desktops and hand held calculators.

A FET is a three-terminal device that uses electric field to control the flow of current. The three terminals are called source, gate and drain. Gate is applied with external voltage to control the current flowing from source to drain. FET is a unipolar device as it operates with the flow of only one type of charge carriers. As the field effect transistor the width of the channel along with the current can be varied with the external electrical field, hence FET is a voltage controlled device. FETs can N-type or P-type channel device.

A FET has three basic terminals. Source: the terminal from which the carrier enters (current denoted by IS). Drain: the terminal from which the carrier leaves the channel (current denoted by ID). Gate: the terminal that modulates the entire channel by applying voltage (current denoted by IG) (sedra, 2003). All the terminals are attached with each other with ohmic contacts. FET can be classified into two types Metal-oxide semiconductor field effect transistor and junction field effect transistors. The basic working principle of a transistor is explained in figure 1.

Figure 1.

Basic principle of a FET device

978-1-7998-1393-4.ch010.f01

The current through the channel from source to drain is controlled through gate by applying the external voltage. The FET’s have their applications in various integrated circuits and as high performance switches the present of metal oxide or dielectric layers FET exhibits high input impedance which makes them more sensitive towards the input signal. Miniaturization of devices in pursuit of faster and portable devices has been the trend of electronics leading to more complex circuits in effect enhancing the performance. This has also made high density memories a reality. As the device size is moving to nanometer regime the circuits and memories will be including nano-scaled transistors, maybe a single molecule transistor that can store data.

The ever-growing electronics industry is based on roadmap predicted by Gordon Moore which states that the numbers of transistors on an integrated circuit will double every year. This roadmap is stated as Moore’s law. This development is pushing electronics into the realm of nanotechnology and in effect approaching silicon wall. So there are limitations on silicon based transistors. The use of nanomaterials in the transistor fabrication offer a very realistic alternate. So there is need to analyze nanomaterials for their electronic properties so as to design Nano-FETs.

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