VLSI Implementation of a High-Speed Pipeline A/D Converter

Introduction

A technology shows the rapid growth leads to evolution in complementary metal oxide semiconductor (CMOS) circuits through reduction in feature size. The majority of complicated systems are combined into a single circuit. Pipeline A/D Converter architecture is regarded as high-speed applications, similar to contemporary signal processing and communication. When related to the SAR A/D Converter architecture, the Pipeline architecture has a significant benefit in terms of high sampling rate. When compared to the Flash A/D Converter architecture, the input capacitance is minimal. High bandwidth and gain operation amplifiers are one of the main building parts in pipeline ADC architecture. It is possible to convert signal processing techniques to the digital domain (Sun & Rahkonen, 2018).

As the technology advances current demands also increases to meet the requirements for a high speed communication. In contemporary mixed-mode digital signal ICs, a medium to high, low-power, and high-speed pipeline A/D Converter architecture is one of the frequently used components. High level circuit integration trends lead to smaller size, more functionality, and lower costs. The primary objective is to adhere to the current on-chip solution trend, which allows digital and analogue circuitry to coexist on a single die using cutting-edge CMOS technology. While modern fabrication technology advantages digital circuits, it presents a significant challenge to analogue circuitry. Less resistance in the amplifier output has an effect on CMOS devices and lowers their analogue performance. Digital signal processing is used in wireless communication systems to make the system design flexible. The AC performance is high in SNDR and SFDR it can achieve more reliability and signal transmission quality. When sampling rates are high and input frequencies are high, it might be difficult for ADC designs to retain high AC performance. Any mismatch and nonlinearity will degenerate the transfer performance as the input sampling frequency increases. To achieve high resolution, a sampling capacitor is essential to decrease noise and to set a bandwidth limit for the incoming signal. Here, creating a sampling front end circuit with low noise and good linearity is crucial. Low skew and low jitter clock generator maintains ADC performance. An analog to digital sub conversion and multiplying digital-to-analog converter (MDAC) are included in each pipeline stage (ADSC). A reconstructed residue is considered for next stages ADSC output is produced by pipelined stage. An entire resolution in A/D converter is considered to cascade their obtained digital codes.