Comparative Performance Analysis of Nanowire and Nanotube Field Effect Transistors

Comparative Performance Analysis of Nanowire and Nanotube Field Effect Transistors

Raj Kumar, Shashi Bala, Arvind Kumar
Copyright: © 2021 |Pages: 17
DOI: 10.4018/978-1-7998-6467-7.ch003
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Abstract

To have enhanced drive current and diminish short channel effects, planer MOS transistors have migrated from single-gate devices to three-dimensional multi-gate MOSFETs. The gate-all-around nanowire field-effect transistor (GAA NWFET) and nanotube or double gate-all-around field-effect transistors (DGGA-NTFET) have been proposed to deal with short channel effects and performance relates issues. Nanowire and nanotube-based field-effect transistors can be considered as leading candidates for nanoscale devices due to their superior electrostatic controllability, and ballistic transport properties. In this work, the performance of GAA NWFETs and DGAA-NT FETs will be analyzed and compared. III-V semiconductor materials as a channel will also be employed due to their high mobility over silicon. Performance analysis of junctionless nanowire and nanotube FETs will also be compared and presented.
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Introduction

In the last few decades, the IC technology industry has seen rapid growth as the feature size of the device has shifted to a nanometer from the micrometer regime to achieve the significant packaging density and remarkable processing speed. However, device size needed to reduce to meet the unceasing demand of having the maximum number of CMOS devices per unit area of an IC. Thus, numerous detrimental effects appear in the switching characteristics of the transistors. Although, some scaling rules are required to follow for decreasing the feature size of the device from one technology node to another to minimize these damaging effects. The Subthreshold characteristics of nanoscale devices deteriorate severely, limit more scaling of conventional MOS transistors. To do continue scaling of ICs along with following the International Technology Roadmap for Semiconductors (ITRS) (ITRS, 2015), (S.M. Sze, 2009), (J.P. Colinge, 2008) there is a need to develop and investigate some other non-conventional CMOS devices. The gate length of MOSFET has reached a sub-22nm regime within a few years. The advanced architectures and materials have been proposed to overcome device scaling concerns. Thereby, the performance of the device gets enhanced for high processing speed, low operating power, and standby power applications (Skotnicki et.al, 2005), (ITRS, 2010), (J.M. Larson and J.P. Snyder,2006),(Colinge et al.,2010),(Kranti et al.,2010),(Goel, et al.,2017).

There are various devices such as FinFET, ultra-thin body-based single, and multiple-gate silicon-on-insulator (SOI) FETs. Then, cylindrical nanowire wrapped in a unique circular gate produces GAA MOSFETs (Y.B. Kim, 2008), (J. P. Colinge, 2028). Although, Si-nanowire GAA MOSFET exhibits tremendous short-channel- effects immunity, some technical issues including a large area of contact and high series resistance refrain its usefulness for ULSI (H.M. Fahad and M.M. Hussain, 2012). Moreover, its drive current is also lower than other MOSFETs (J. Dura et al., 2011), (Autran et al., 2005). In contrast to that, a novel silicon-nanotube (Si-NT) FET has been proposed, fabricated, and investigated, maybe a worthy option for future ULSI (D.Tekleab, 2014), (Tekleab, et al.,2012). The Si-NT FET consists of a tube based Si-channel surrounded by a cylindrical shell (outer) and core (inner) gates. It has tremendous short-channel effects immunity attributed to the presence of two gates, responsible for volume inversion. Thereby, it possesses excellent ON and OFF state electrical characteristics (Fahad et al.,2011), (Tiwari et al.,2016), (Kumar et al.,2017),(Scarlet et al.,2017).

In this work, a performance comparison of Nanotube-NT and nanowire-NW FETs has been presented. The variation effect of the design parameter of both NT and NW FETs have been Compared. This analysis has been carried out for various gate dielectrics i.e. SiO2 and HfO2. High-k Gate oxide material and its thickness affect the performance of the device by decreasing leakage current and suppressing short channel effects (SCEs) (Baidya et al., 2016).High- k gate oxide devices can be used in future technologies for CMOS circuit applications.

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