A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate

A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate

Vandana Shukla (Amity School of Engineering and Technology, Amity University Lucknow Campus, Lucknow, India), O. P. Singh (Amity School of Engineering and Technology, Amity University Lucknow Campus, Lucknow, India), G. R. Mishra (Amity School of Engineering and Technology, Amity University Lucknow Campus, Lucknow, India) and R. K. Tiwari (Department of Physics and Electronics, Dr. Ram Manohar Lohia Avadh University, Faizabad, India)
DOI: 10.4018/IJBDCN.2015010104
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Abstract

In the recent scenario of microelectronic industry, the reversible logic is considered as the burgeonic technology for digital circuit designing. It deals with the aim to generate digital circuits with zero power loss characteristics. Optical computing, Nanotechnology, Low power CMOS design and Digital Signal Processing (DSP) processors are leading areas of development with the concept of reversible logic. Researchers have already proposed various subsystems of the computer for the creation of low power loss devices with the help of numerous available reversible logic gates. Here in this paper, the authors have proposed a new reversible gate named as CDSM gate with 4×4 size. This CDSM gate is used to design optimized 4-bit binary comparator. The optimization is improved as compared to the existing designs based on some significant performance parameters such as total number of gates, garbage outputs generated, constant inputs and quantum cost. Comparators are widely used in various computing applications such as counters, convertor, Central Processing Unit (CPU) and control circuits etc. The comparator circuits using reversible logic can be visualized as a low power loss subsystem for the development of improved digital systems.
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1. Introduction

Earlier, digital circuit designs were carried out with the help of conventional logic gates. These conventional logic gates are generally irreversible in nature due to the tendency of bit loss during the operation. Conventional logic gates are characterized with lesser number of output signals as compared to the total number of input signals. For example, there is only one output signal out of two or more inputs in an AND gate. Now employing this AND gate in any digital circuit information loss occurs due to the bit loss during the operation which leads to the power loss from the digital device. Only NOT gate can be categorized as reversible gate (size 1×1) among the existing conventional gates.

In 1961, R. Landauer calculated that for single bit loss, the device dissipates kTln2 joules of energy, where k is the Boltzmann constant (approximately 1.38 X 10-23 J/K) and T is the temperature of the device in Kelvins (Landauer, 1961). This energy dissipation will lower the entropy of the system, which will lead to the heat generation by the device during the operation. Well ahead in 1970, G. Moore predicted his legendary concept called as Moore’s observation (Moore, 1965). Moore’s observation states that the number of design units for an electronic system roughly doubles for unit area in the time span of two years. This phenomena leads to the exponential growth in the heat generation or information loss through the electronic devices.

Later in 1973, C. H. Bennett has shown that this energy loss can be diminished or even detached from the digital system with the help of reversible concept and pointed out that the minimization of bit loss from the digital systems can be achieved by replacing conventional design entities with the reversible design entities (Bennett, 1973).

Subsequently researchers started exploring in the area of designing digital logic circuits with the help of reversible logic (Frank, 2005; Kemtopf, 2002). Earlier some basic reversible logic gates were proposed, with the help of these gates some combinational circuits of the computing devices were designed using reversible logic. Now various memory, control and processing parts of the computing system are being targeted by the reversible researchers. It is a tedious task to design ideal reversible circuit of any digital system due to the limitations upon the optimization of various performance parameters. So now designers are working in the field of achieving most optimized reversible design of the target digital circuit (Kant, 2012; Vasudevan, 2006).

Among combinational digital circuits, binary comparator circuits are one of the most worthwhile subsystem. Magnitude comparators are used to provide comparative association of two binary numbers. These circuits are utilized in devices that measure and digitize analog signals, subsystems of Arithmetic Logic Unit (ALU) and control circuits etc. While designing a four bit comparator circuit through conventional approach, we require eight input signal bits (four bit for first binary number and another four bits for second number to be compared) and it generates only three output signals. So there is some information loss caused due to the loss of five bits. Reversible designing approach demands that ideally this comparator circuit should be designed using minimum number of reversible logic gates. Here we have improved existing designs for four bit binary comparator circuit with the help of optimization of few selected performance parameters.

This paper presents a new reversible logic gate named as CDSM gate. Here CDSM gate is used to design an optimized four bit binary magnitude comparator circuit. This reversible logic gate can be further utilized to design other low loss digital circuit with reversible logic.

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