A Proposed Novel Description Language in Digital System Modeling

A Proposed Novel Description Language in Digital System Modeling

Péter Horváth (Budapest University of Technology and Economics, Hungary), Gábor Hosszú (Budapest University of Technology and Economics, Hungary) and Ferenc Kovács (Budapest University of Technology and Economics, Hungary)
Copyright: © 2015 |Pages: 15
DOI: 10.4018/978-1-4666-5888-2.ch686
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The increasing complexity of data-processing systems forced the design methodologies to move to a higher abstraction level (Shin, Gerstlauer, Dömer & Gajski, 2008) than the traditional register-transfer level (RTL). In the 2000s the so-called electronic system level (ESL) paradigm was evolved including the system level description languages, such as SystemC, SystemVerilog and the high-level synthesis (HLS) tools, such as SystemCrafter and Catapult-C, which are able to transform an algorithmic model into a gate level description (Casseau & Le Gal, 2012; Kim & Liu, 1995). However, at the design process of the instruction set processors the HLS method cannot be used efficiently because the main structure of the microprocessors does not fits well with the data-processing model of the digital signal processing systems, which HLS is optimized for.

Presently, the architecture description languages (ADLs) are the high-level tools of instruction set processor design. These languages can describe the functionality of the system on the behavioral level but, as opposed to the languages used in the HLS method, they can describe the structure of the system as well in the same model. Even in case of ADLs designers usually have to deal with significant restrictions in terms of microarchitecture and they are not able to model application-specific functional units with dedicated functionality.

In this article we present a novel approach of register-transfer level hardware modeling based on a new hardware description language called Algorithmic Microarchitecture Description Language (AMDL), which combines the advantages of HLS-based and ADL-based design approaches. It provides an algorithmic-style design entry and in the same time it makes possible to manage the exact register-transfer level structure of the designed system.

The article is organized as follows. Section 2 gives a brief overview of concept of high-level synthesis and architecture description languages and presents the HDL representations of the register-transfer level models, which play a considerable role in the hardware synthesis methodologies. Section 3 gives a detailed presentation of a novel hardware modeling language including its scope and objective, language constructs, model structure and design examples. Finally, Section 4 presents a case study consisting of two application-specific instruction set processors, which were designed with the proposed design method.

Key Terms in this Chapter

Application-Specific Instruction-Set Processor (ASIP): A stored-program machine with a special instruction set optimized for a specific application or application domain.

Instruction-Set Architecture (ISA): An abstraction level typically used by the compiler designers and the system programmers of the microprocessors.

Microarchitecture: The functional units and their connections which constitute the datapath of the digital data-processing system.

Structural RTL: An abstraction level in the digital system modeling represented with a fine-frained HDL implementation.

Architecture Description Language (ADL): A special HDL optimized for instruction set processors.

Behavioral RTL (Register-Transfer Level): An abstraction level in the digital system modeling represented with a coarse-grained, behavior-like HDL implementation.

High-Level Synthesis (HLS): A procedure which is able to transform a high-level algorithmic description into a gate-level representation of the digital circuit implementing the described functionality.

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