Dynamic Reconfigurable NoC (DRNoC) Architecture: Application to Fast NoC Emulation

Dynamic Reconfigurable NoC (DRNoC) Architecture: Application to Fast NoC Emulation

Yana E. Krasteva (Universidad Politécnica de Madrid, Spain), Eduardo de la Torre (Universidad Politécnica de Madrid, Spain) and Teresa Riesgo (Universidad Politécnica de Madrid, Spain)
DOI: 10.4018/978-1-61520-807-4.ch009
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Abstract

The aim of this Chapter is to present a highly flexible reconfigurable NoC solution for commercial FPGAs on one side, and on the other side, to provide an innovative approach for fast NoC emulation. The reconfigurable on-chip communication solution that is proposed in this chapter is capable of being reconfigured by means of adapting routers, network interfaces and cores themselves. The main distinguishing characteristic of the presented on-chip communication approach is that it permits to distribute the available on-chip communication resources among different communication topologies and thus, independent and application specific communication strategies can coexist and run in parallel. Furthermore, the proposed solution is not limited to NoCs and it permits to build a vari ety of on-chip communication. The proposed method in this Chapter for fast emulation provides a rapid way of validating different communication alternatives. The emulation method is based on the original idea of hard core re-usability through the exploitation of partial reconfiguration capabilities of some state of the art FPGAs. Both aspects have been tested and validated using a proof of concept approach and are discussed along this Chapter.
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Introduction

Reconfigurable Systems on Chip (RSoCs) bring flexibility and adaptability to meet the demanding requirements of the electronic market. The most common topology for reconfigurable systems is the combination of an Field Programmable Gate Array (FPGA) and microprocessor(s), either embedded on the same device or separated in different packages. Some FPGA devices include Digital Signal Processing (DSP) related blocks, like embedded multipliers, memories and microprocessor cores, which facilitate the mapping of complex functions. Even more, some FPGAs are able of being partially reconfigured, that is, to change the configuration memory of a part of the FPGA while the rest is kept active. This feature takes the powerful benefits of reconfigurability to a much higher level and permits to overcome restrictions related to long configuration times and performance losses when reconfiguring the entire device.

Partial run-time reconfigurable systems permit to keep different cores (tasks) running on the hardware and change/update them when needed without affecting other cores in the FPGA.

In a reconfigurable system, tasks may be loaded, unloaded or relocated to other FPGA areas without previous knowledge of what will be the future combination of cores and dependencies among them. Therefore, considering this evolving situations, on-chip communication solutions that are suitable in a given moment may not be the most adequate in other conditions (due to traffic changes, application updates, etc.). In such changing environment, communications reconfiguration is an important issue that may lead to better exploitation of on-chip resources and increased device performance. The communication reconfiguration process should be enabled and carried out without affecting other cores data exchanges, and data losses must be avoided even for the part that is being reconfigured.

The communication reconfiguration problem can be tackled from several points of view, focused on solving different system design problems. From higher levels systems modeling, trough system flexibility control usually based on extending operating systems, to system architecture and low level reconfigurability control. In this chapter, the problem is tackled from the system architecture and the system reconfigurability points of view and provides real implementations of the proposed solutions that have been tested with core models. First, a brief state of the art is included along with a problem statement, and then, a solution that goes beyond NoCs by providing an on-chip communication adaptation solution is described in detail. The proposed solution covers several aspects: a communication architecture definition, along with its implementation on an FPGA and the definition of a router and a packet format that support system reconfigurability. Additionally, while describing the adopted solution, several reconfigurability aspects, performed tests and practical implementation issues will be presented. Conclusions, analysis and discussions of the discovered problems and achieved reconfiguration results are also included in the chapter. After that, in the second part, the adopted architecture and design solutions are integrated in an emulation framework, which is based on the innovative idea of exploiting hard core reusability through partial reconfiguration, for fast emulation of RSoCs, is described in detail. Three use cases, based on core models, have been implemented for proving the emulation approach and achieved speedup reports are included at the end of the Chapter.

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