High Level Transformation Techniques for Designing Reliable and Secure DSP Architectures

Introduction

Reverse Engineering (RE) has become a serious threat to the silicon industry. To overcome this threat the IC's needed to be made secure and non-obvious in order to find their functionality with their architecture. Real-time signal processing algorithms need to be faster and more reliable. Adding up additional circuit for increasing the security of the IC is not permit-able due to an increase in overhead of the IC. In this chapter, we introduce a few High-Level Transformations (HLT) which are used to make the circuit more reliable and secure against reverse engineering without having overhead on the IC.

With the sudden blast in smart devices in our home, work, military services it has come into notice that software is not the only thing that needs protection (Anderson, 2006). The gigantic use of IC chips in all devices and the optimum use of the functionality of devices has to lead to increasing in the number of transistors in the chip parabolic-ally as predicted in called as Moore’s Law. The increase in chip density results in decreases in the size of the chip (Iqbal, Potkonjak, Dey, Parker, 1993). This decrease in the range of 6nm-7nm has to lead to the design and fabrication of IC chips as a tedious and time-consuming task. This has resulted in the development of various outsourcing companies for Fabrication, Masking, and IP generation task. The increase in outsourcing (Lao & Parhi, 2015) of the chips has made the designer lose his/her control in his design. The security of the IC chips can be breached at many levels. There has been a tremendous increase in cases of Hardware theft. This demand for a method to provide protection against Hardware Theft and Reverse Engineering attacks. This paper deals with a technique called Obfuscation. Obfuscation is a technique of making the design functionally and structurally tedious to reverse engineer. A VLSI circuit designed by an engineer, re-sed by several other people. The circuit is available in various format like RTL/SOC/ASIC (J. Zhang, 2013). This circuit can be protected in order to avoid malpractice. This architecture can be protected by means of intestate property (IP). VLSI industry pays millions of dollars to keep their IP safe. There are two types of IP exits (Moore, 1998) (1) Hard IP and (ii) Soft IP. Soft IP is synthesizable register transfer level (RTL) while Hard IP contains (GDSII format) IC which can be used for direct implementation. Vendors provide these IP on purchase with an agreement for authenticates use. (Gu & Zhou, 2019) A different method of IP protection is (a) legal means such as patent, copyright and trade (b) license agreement and encryption technique (c) determining unauthorized means of usage like hardware watermarking. Addition of IP protection technique enhances the circuit cost but increase the security level; but their severe threat in VLSI industry to protect their IP. Misuse of the IP leads to heavy loss of revenue, it is reported that industry going in loss more than 10000$/per year. There are following mechanism through which data is stealing from hardware of the circuit. Only software mechanism is not sufficient to protect the IC. A complex combination of encryption technology and few hardware based features incorporated.

• 1.

  IP Piracy: A person or firm purchase IP from a vendor and create another copy by cloning. After making a few changes the sell to another firm ar higher cost (Zhou, 2017).

• 2.

  The untrusted firm makes an illegal copy of GDSII (Hard IP) and sells to another firm,

• 3.

  Untrusted foundry manufacturer sells IP at different brand

• 4.

  Adversary performs post-silicon reverse engineering on IC to create a clone.

• 5.

  The designer may misuse the IP during design

• 6.

  While an IP is a communication with the other IPs on SoC, those may extract valuable information from that IP.

• 7.

  Adversary may misused the IP while SoC communicates with remotely hardware

• 8.

  Hardware trojan horse (HTH) (Li & Lach, 2018), (Potkonjak, Nahapeti, Nelson & Massey, 2009) based attack leaks side-channel information while ASCI/SOC perform computation in term of power, delay, radiation, etc.