A NoC-Based Infrastructure to Enable Dynamic Self Reconfigurable Systems

A NoC-Based Infrastructure to Enable Dynamic Self Reconfigurable Systems

Leandro Möller (Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Brasil), Ismael Grehs (Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Brasil), Ewerson Carvalho (Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Brasil), Rafael Soares (Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Brasil), Ney Calazans (Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Brasil) and Fernando Moraes (Pontifícia Universidade Católica do Rio Grande do Sul (FACIN-PUCRS), Brasil)
DOI: 10.4018/978-1-61520-807-4.ch001
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Abstract

Platform-based designed SoC includes one or more processors, RTOS, intellectual property blocks, memories and an interconnection infrastructure. An associated advantage of processor is flexibility at the software level. Hardware is not flexible. Thus, dedicated IP blocks must be inserted at design time. An alternative is to provide the platform with reconfigurable hardware blocks with sufficient capacity to implement any envisaged dedicated IP block. Dynamic self-reconfigurable systems (DSRSs) introduce flexibility to hardware. In DSRSs, IP blocks are loaded according to application demand, an approach that potentially reduces area, power consumption and total system cost. Platform-based design associated to dynamic reconfiguration techniques provide both hardware and software flexibility. The contributions of this work are: (i) DSRS architecture proposal; (ii) straightforward DSRS design flow for this architecture; (iii) NoC specifically designed to support dynamic hardware reconfiguration; (iv) two proof-of-concept case studies. Results point that among the best implementation choices for DSRS are those that employ NoCs as communication infrastructure, adopt the use of software configuration controllers, make use of unidirectional LUT-based IP interfaces and dispose of an internal port for reconfiguration.
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This Section provides a historical landscape of the state of the art in reconfigurable devices, processors and systems using the timeline of Figure 1. A previous review on reconfigurable architectures can be found in (Hartenstein, 2001), while reconfigurable processors are reviewed in (Barat et al., 2002).

Figure 1.

Reconfigurable technology evolution: systems, processors and devices

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