Reduction of the Transferred Test Data Amount

Introduction

After the era of ad-hoc DFT techniques, designers found that it is necessary to formalize the principles that improve observability and controllability of flip-flops in the design. This development resulted in adopting serial test data access mechanism as a standard for improving testability of large circuits. The random access scan methods were not adopted in industrial designs because of their complicated routing structure. Scan testing simplifies creating a test set in the ATPG, and thus it helps keeping the cost to remain acceptable. The scan chain insertion was first used in 1980s, when the IC technology was limited mostly by the gate delay and no other hardware that could reduce the amount of transferred data was acceptable. Scan access is guaranteed by adding a test mode to the flip-flops, in which all or a part of them form one or more shift registers. This solution uses only a limited number of IC pins for reading and/or setting internal flip-flops and enables designers to generate test sets only for a combinational part of the designed circuit, which is much easier than testing complex automata behavior. The flip-flops need not to be tested separately, as by shifting the flip-flops and capturing the combinational part outputs all their functionality is exercised. The serial testing mechanism was adopted also for testing complex boards. The IC boundary pins were equipped with a flip flop with a possible functionality of a shift register. The boundary scan design makes testing of printed circuit board wire connections easier and enabled also using standard, non adapted IC test even for ICs soldered on the board. The next step in improvement of the observability and controllability of SOC circuits was done, when the serial scan registers were added into the SOC circuits, where they separate different cores. The core wrappers are standardized, and they enable designers to test each core separately by using non adapted test sets. The hardware overhead of the scan chain test access mechanism is relatively big, but it is not crucial as the nowadays technologies provide enough of transistors.

With the growing complexity of tested circuits, the length of the scan chains that guarantee the serial test data access have grown up, and thus IC testing became unacceptably long and expensive. The relative cost of testing has become one of the major problems of IC manufacturing. In 1990s, the technology moved to smaller geometries, and the inter gate delay became more critical than the intra gate delay. The growing number of transistors on a chip caused that the cost of manufacturing a transistor has decreased. Because of higher quality demand (zero defect per million), the cost of testing has stayed relatively constant. The pressure on further cost reduction caused that low-cost ATEs are nowadays used. The amount of transferred data became to be critical because of the Test Access Mechanism (TAM) insufficiency. The hardware expensive solutions that could reduce the transferred data amount became useful, and this fact encouraged researchers to develop new test compression methods. The nowadays compression and decompression systems reduce the necessary bandwidth of the TAM and facilitate using the low cost ATEs (Kapur R., Mitra, S., Williams, T.W., 2008). The test time is reduced by using several parallel scan chains that are fed with patterns decompressed in a decompressor that guarantees a variable setting of the parallel scan chain bits (Figure 2).

Figure 2.

Mixed mode BIST with modified TPG sequence