SpaceWire Inspired Network-on-Chip Approach for Fault Tolerant System-on-Chip Designs

Introduction

In this chapter a specialized Network-on-Chip approach is presented, which logically isolates a host system from reconfigurable modules: System-on-Chip Wire (SoCWire). First the conditions for SRAM-based FPGAs in space environment are introduced. Then, the Virtex-4 hardware architecture is outlined to understand the fault behavior due to radiation or during the dynamic reconfiguration process. Furthermore dynamic partial reconfiguration in Virtex-4 is presented and limitations of a bus structure are discussed. Finally, a fault tolerant Network-on-Chip approach, SoCWire is presented and its performance is outlined.

Data Processing Units (DPUs) on-board of spacecrafts are used as interface between spacecraft and several instrument sensor electronics or heads, providing the operational control and specific data processing of scientific space instruments. These systems have to provide sufficient computer power at low volume, mass and power consumption. Furthermore these instruments have to be suitable for the harsh space environment conditions (e.g. temperature, radiation). They need to be robust and fault tolerant to achieve an adequate reliability at moderate unit costs. Different implementation approaches for DPUs exist in traditional designs (i) based on rad-hard discrete components, (ii) Application-Specific integrated Circuits (ASICs) of high quality and (iii) Commercial Off-The-Self (COTS) devices. The major disadvantage of these three approaches is reduced design flexibility. A change in a specific data processing algorithm results in a major hardware design change (Fiethe, Michalik, Dierker, Osterloh, & Zhou, 2007). The Configurable System-on-Chip (CSoC) approach is based on radiation tolerant SRAM-based FPGAs and provides the capability for both flexibility and reliability. The suitability of this approach was successfully demonstrated in many space missions (Osterloh, Michalik, Fiethe, & Kotarowski, 2008). But the reconfigurability of SRAM-based FPGA has only been used in the development phase. A further enhancement of this approach would be to use the partial and dynamic reconfiguration capability of these devices in-flight. Processing modules could be updated, which is especially an improvement for DPUs in space because of the non-accessibility of maintenance points. Furthermore processing modules could be updated to improve functionality e.g. a generic data compression core can be replaced by a sophisticated core to calculate scientific parameters directly in-flight. Dynamic partial reconfiguration enables run-time adaptive functionality and is an improvement in terms of power, device utilization and device count. To achieve theses advanced design goals the system requirements for high reliable space applications have to be considered. DPUs are exposed to the harsh space environment. Radiation has a major impact on the system and can lead to functional interruption. Therefore mitigation techniques e.g. Triple Modular Redundancy (TMR) in combination with configuration scrubbing are required. Another important requirement for DPUs is the system qualification. The system is qualified on ground by intensive stress-tests. This qualification has to be guaranteed in space even after a module update or during the dynamic reconfiguration process. Therefore the modules need to be isolated from the host system logically and physically. Detailed knowledge of the hardware architecture is necessary (i) to indentify effects during the dynamic reconfiguration process and fault behavior caused by radiation and to (ii) apply appropriate mitigation techniques.