What is FPGA (Field Programmable Gate Array)

In this chapter, the authors present a new scheduling algorithm that brings a reduction in dynamic power consumption by achieving components scheduling while holding the global latency of the application. The main idea of that algorithm is to augment the latency of some components without impacting the dependency constraint and degrading the global latency of the system. There exist many solutions that manage to increase component's latency; one of them is through decreasing the frequency of their corresponding clocks. Generally, such a method leads to an augmentation in global latency of a system. However, this algorithm manages to reduce the consumed power and hold the same global latency of the system. The presented algorithm has been tested and it provides a significant gain in power at both simulation and physical levels.